London, United Kingdom
, have done Masters degree in Microelectronics from one of the best UK university. Previously I have obtained an Electrical Engineering degree. I worked mostly with digital signal processing, reconfigurable hardware design, and advanced VLSI design. Though I am new here, but I can assure you that you will not get a chance to complain.
My top sides are
- Digital system design
- High Speed PCB Design
- FPGA design/ ASIC design
- Analogue Electronics - digital signal processing - Image & video processing - system on chip
- Embedded System Design
Recently worked with esp32, raspberry pi, microblaze, image nano, Sitrra, armA9 dual core, Ardino and stm32.
For fpgas I worked with all the brands such as intel, xilinx, lattice. I have also worked in manufacturing a chip for satellite communication. I have recently design a board with speed upto 4ghz and with a lot of different chips.
Ongoing relation / part-time
• Design included from component selection, high speed PCB design (tracks upto 5GHz), obtaining
signal and power integrity. Doing ibis model simulation analysis. Deliver board to fabrication and tune it according to the requirements.
• Design the firmware in VHDL and test it with test bench, test it with hardware, obtain timing
requirements by using static timing analysis, interfacing with external IPs, cross clock domain data
transfer and DSP algorithm implementation.
• Developed the PC software using DLL file, making the functions and deliver it.
• Designed schematic and eight-layer PCB involving highspeed camera, USB-C 3, SPI master
and slave, DDR2 and SD card interface. Signal integrity was obtained by using ibis models
simulation. Power supply was designed, and target impedance was obtained using LTspice
Cyclone-V FPGA was used to read out the images data. DDR2 IP was generated and interfaced with camera via cross clock domain. The ram is read by USB-C at 5 Gbps. DDR2
RAM used to store the image data to handle the pixel speed. Images and some control values
stored in the SD card. Some DSP algorithms were also been implemented. The main
architecture is to read these images. Put these images in DDR2 RAM. Send them to PC. And
write the SD card with these images. The user can use this board as slave over SPI interface and excess images. FPGA design implemented in VHDL. For test benching some models
were made. Timing constraints were met, and some were fixed through pipelining. Cross
clock domain was also done.
• Designing a scalar having 2d FIR filter of an order of 3 and a decimator to reduce the picture size by a factor of 2.
• Insync Technology Junior Firmware (Software / Hardware) Design
• Producing RTL design, analyzing it through timing diagrams. Estimating FPGA resource
• Using VHDL to implement this proposed design. Test benching in Modelsim. Proposing tester
architecture and performing tests in the testbench. Testing on hardware using logic analyzer.
Using testing points for testing on hardware.
• Using Python to automate design procedure.
• Designed Features on FPGA:
• Designed generic ROM reader. The main purposeto generate sync flags for HDMI
IP to support different video standards.
• Designed panning for test patterns. Creating a fix offset per frame to create fixed
speed on the screen.
• Designed timecode conversion and supported multichannel. Creating pipelining to reduce resource utilization.
BSc, Electrical Engineering
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