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Highly experienced C/C++/Python Software Engineer with real-time and machine learning specialisms
Jonathan Lucas
,
BRISTOL, United Kingdom
Experience
Other titles
Skills
I'm offering
A highly experienced software engineer specialising in real-time embedded and cloud-based systems. I have several decades of management and development experience with a proven track record of delivering highly complex multidisciplinary projects successfully to market from the ground up.
Markets
United Kingdom
Links for more
Once you have created a company account and a job, you can access the profiles links.
Language
English
Fluently
Ready for
Larger project
Ongoing relation / part-time
Full time contractor
Available
My experience
2017 - ?
job
Cofounder & Director
Folio Intelligence.
• Implemented a fully automatic financial trading pipeline connecting to Interactive Brokers' gateway API.
• Implemented cloud-based simulation framework for the above on AWS using docker containers and batch execution for parameter optimisation (using quadratic programming) and/or grid searches.
• Designed and implemented a Python framework used for all input data for the Folio system, using a MySQL database hosted on AWS as the intermediate local data store and a generic import mechanism to allow multiple ultimate data sources.
• Set up Gitlab/AWS based full continuous integration/continuous deployment setup for deployment of Folio's algorithms.
• Implemented cloud-based simulation framework for the above on AWS using docker containers and batch execution for parameter optimisation (using quadratic programming) and/or grid searches.
• Designed and implemented a Python framework used for all input data for the Folio system, using a MySQL database hosted on AWS as the intermediate local data store and a generic import mechanism to allow multiple ultimate data sources.
• Set up Gitlab/AWS based full continuous integration/continuous deployment setup for deployment of Folio's algorithms.
Python, Algorithms, Docker, AWS, Database, Cloud, Deployment, Integration, Framework, UP, It infrastructure, Sql, DevOps, Git, Financial technology
2015 - 2017
job
Cofounder & Technical Director
Five AI.
• Designed and implemented Five AI's first working convolutional network (https://www.dropbox.com/s/oolzq860s5yisir/JOLU.mp4?dl=0), a state of the art real-time single forward-pass object detector and classifier using the Torch7 framework. Led the team to implement this and a generic training framework in Tensorflow, and then extend it to add pixel-level segmentation output.
• Set up the ROS-based software architecture framework and wrote many of the low-level drivers for the first proof of concept vehicle.
• Implemented pure-pursuit and proportional path tracking control schemes for the vehicle.
• Implemented a mixture model in Python/numpy to explain daily traffic flows for a data analytics project.
• Wrote and implemented all of the software engineering processes, including CI systems using Gitlab and a small server farm.
• Set up and maintenance of the company multi-site IT infrastructure.
• Set up the ROS-based software architecture framework and wrote many of the low-level drivers for the first proof of concept vehicle.
• Implemented pure-pursuit and proportional path tracking control schemes for the vehicle.
• Implemented a mixture model in Python/numpy to explain daily traffic flows for a data analytics project.
• Wrote and implemented all of the software engineering processes, including CI systems using Gitlab and a small server farm.
• Set up and maintenance of the company multi-site IT infrastructure.
Software, C/c++, Python, Lua, Robotics, Engineering, Processes, Framework, Server, Ai, Deep learning, Convolutional Neural Network, Infrastructure, It, Architecture, Network, Tensorflow, Analytics, Software engineering, It infrastructure, Training, Software Architecture, Management
2011 - 2015
job
Director
NVIDIA.
• Director of a multi-site, multidisciplinary team of 50 engineers split into 5 sub-teams, responsible for implementation, verification and test of the NVIDIA cellular modem's physical
layer, supporting 4G Category 12 FDD-LTE and TD-LTE (datarates of up to 600Mb/s) and 3G Category 24/6 HSPA+ (UMTS and TD-SCDMA)
o 2G class 33 GSM/GPRS/EDGE.
• Delivered this modem to mass production for many phone and tablet platforms (including LG G2 Mini, Wiko Wax, Microsoft Surface 2 RT and the NVIDIA Tegra Note 7).
• Responsible for Capex budget of ~£5m pa and Opex of ~£2.5m pa.
• Leader of NVIDIA's i500 modem chipset bring-up activity from FPGA-based verification through to initial silicon bring-up.
• Responsible for physical layer bring-up of the modem subsystem of the Tegra 4i SoC (cat4 LTE, cat24/6 HSPA+. Class 33 2G)
• Software representative in the next-generation chip architecture team (i1000).
• Responsible for delivery of all modem software for i1000 project.
• Integration of physical layer tests into a Jenkins-based fully automatic continuous-integration test system, which verifies software changes against bit-exact simulations, real-world test systems and live networks on a per-change and scheduled basis.
layer, supporting 4G Category 12 FDD-LTE and TD-LTE (datarates of up to 600Mb/s) and 3G Category 24/6 HSPA+ (UMTS and TD-SCDMA)
o 2G class 33 GSM/GPRS/EDGE.
• Delivered this modem to mass production for many phone and tablet platforms (including LG G2 Mini, Wiko Wax, Microsoft Surface 2 RT and the NVIDIA Tegra Note 7).
• Responsible for Capex budget of ~£5m pa and Opex of ~£2.5m pa.
• Leader of NVIDIA's i500 modem chipset bring-up activity from FPGA-based verification through to initial silicon bring-up.
• Responsible for physical layer bring-up of the modem subsystem of the Tegra 4i SoC (cat4 LTE, cat24/6 HSPA+. Class 33 2G)
• Software representative in the next-generation chip architecture team (i1000).
• Responsible for delivery of all modem software for i1000 project.
• Integration of physical layer tests into a Jenkins-based fully automatic continuous-integration test system, which verifies software changes against bit-exact simulations, real-world test systems and live networks on a per-change and scheduled basis.
C, Python, Software architecture and design, Jenkins, Integration, Test, Architecture, Implementation, Software, Gsm, FPGA, Production, Project Management, Budget, Management
2004 - 2011
job
Physical Layer Scheduler Team Manager
Icera.
• Design and implementation of various parts of the Icera tri-mode physical layer scheduler code, including the 3G finger manager, uplink chain (encoding and spreading) and measurement
subsystem.
• Leadership & recruitment of physical layer scheduler team (expanded from a single-site 5 person team to 20 people across 2 sites).
• Responsible for implementation of the physical layer scheduler subsystem of three generations of the Icera multi-mode cellular modem, supporting 2G (GSM/GPRS), 3G (UMTS HSPA+) and
4G (LTE-FDD) radio access technologies at datarates of up to 75Mb/s.
• Responsible for physical layer product approval for many (>20) products based on these chipsets. This requires passing GCF, IOT and customer/operator acceptance tests on most major world cellular networks (including Softbank JP, AT&T, T-Mobile, Vodafone and Orange).
• Design and implementation of an RTOS for the Icera chipset family and equivalent OS abstraction layer for Windows and Linux.
• Design and implementation of real-time logging system for the Icera modem. Also implemented multi-platform (Linux/win32) decoder and visualisation GUI (C and Python) for this.
• Design and implementation of company build system using make.
• Creation of guidelines for and oversight of migration of source control management system from CVS/Gnats to a fully integrated system based on Bugzilla and Perforce.
subsystem.
• Leadership & recruitment of physical layer scheduler team (expanded from a single-site 5 person team to 20 people across 2 sites).
• Responsible for implementation of the physical layer scheduler subsystem of three generations of the Icera multi-mode cellular modem, supporting 2G (GSM/GPRS), 3G (UMTS HSPA+) and
4G (LTE-FDD) radio access technologies at datarates of up to 75Mb/s.
• Responsible for physical layer product approval for many (>20) products based on these chipsets. This requires passing GCF, IOT and customer/operator acceptance tests on most major world cellular networks (including Softbank JP, AT&T, T-Mobile, Vodafone and Orange).
• Design and implementation of an RTOS for the Icera chipset family and equivalent OS abstraction layer for Windows and Linux.
• Design and implementation of real-time logging system for the Icera modem. Also implemented multi-platform (Linux/win32) decoder and visualisation GUI (C and Python) for this.
• Design and implementation of company build system using make.
• Creation of guidelines for and oversight of migration of source control management system from CVS/Gnats to a fully integrated system based on Bugzilla and Perforce.
C, Python, Linux, Design, Leadership, Management, Iot, Windows, Radio, Recruitment, Implementation, Mode, Gsm, Perforce, Manager
1999 - 2004
job
Technical Expert
UbiNetics Ltd.
• System architect and technical authority for L1SW for a multi-mode 384kb/s capability class 3G SoC chip set design.
• Design and implementation of an ASN.1 compiler using lex/YACC, producing platform-independent C-based codecs suitable for the 3G Access Stratum.
• Design, implementation, test and support of an RTOS abstraction layer, incorporating a distributed processing model, a generic IO layer and a sophisticated logging mechanism. Supervision and implementation of a C source-level signal logging and scripting based GUI test tool to complement this system.
• Design and implementation of a V.42bis compression engine.
• System architect for DSP software for a full 3G 384kbps rack-mounted test mobile (both cdma2000 and UMTS). Included design and implementation of a distributed RTOS for use on a DSP board.
• Recruitment and management of 12-man DSP group.
• Design and implementation of an ASN.1 compiler using lex/YACC, producing platform-independent C-based codecs suitable for the 3G Access Stratum.
• Design, implementation, test and support of an RTOS abstraction layer, incorporating a distributed processing model, a generic IO layer and a sophisticated logging mechanism. Supervision and implementation of a C source-level signal logging and scripting based GUI test tool to complement this system.
• Design and implementation of a V.42bis compression engine.
• System architect for DSP software for a full 3G 384kbps rack-mounted test mobile (both cdma2000 and UMTS). Included design and implementation of a distributed RTOS for use on a DSP board.
• Recruitment and management of 12-man DSP group.
Design, C, Scripting, Management, Test, Recruitment, Implementation, Support, Supervision, Set design, Software, Mode, DSP, Processing
1998 - 1999
freelance
Principal Consultant
PA Consulting Group.
• Team leader (5- to 9-man team) for DSP software design for multi-standard (CDMA-2000 and 3GPP capable) W-CDMA test mobile using 8 C6x DSPs incorporating a rake receiver and Turbo/Viterbi channel codecs.
• Member of DSP software team for UMTS test mobile demonstrator for Motorola. This demonstrated a UMTS air link transporting live streaming video data and IP services at the GSM World Congress.
• Line management responsibility for DSP group within practice.
• Member of DSP software team for UMTS test mobile demonstrator for Motorola. This demonstrated a UMTS air link transporting live streaming video data and IP services at the GSM World Congress.
• Line management responsibility for DSP group within practice.
C, DSP, Design, Video, Management, Test, Technology, Software design, Software, Gsm, Streaming
1994 - 1998
freelance
Consultant
The Technology Partnership.
• Project leader for full GPRS protocol stack development (including L1, RLC-MAC, MM, LLC, SNDCP, SM, GSMS, PPP and AT interface modules). Project team of 7-10 people, budget £4m.
• Member of design team for next generation ADI/TTP mobile communications chip set.
• ICO data stack development work as a follow-up to project below.
• Project leader for GSM data services software, including full system design, implementation of transparent data and fax modules, FTA and field testing.
• Team member for FTA on several commercially available GSM handsets based on projects below.
• Designed and implemented audio subsystem on DSP (ADSP2171 native assembler).
• Designed and implemented layer 1 idle mode subsystem (C, on an H8 micro-controller running Hitachi proprietary RTOS).
• Implemented GSM SIM driver.
• Extensive on-site support of various clients for all of the products above.
• Member of design team for next generation ADI/TTP mobile communications chip set.
• ICO data stack development work as a follow-up to project below.
• Project leader for GSM data services software, including full system design, implementation of transparent data and fax modules, FTA and field testing.
• Team member for FTA on several commercially available GSM handsets based on projects below.
• Designed and implemented audio subsystem on DSP (ADSP2171 native assembler).
• Designed and implemented layer 1 idle mode subsystem (C, on an H8 micro-controller running Hitachi proprietary RTOS).
• Implemented GSM SIM driver.
• Extensive on-site support of various clients for all of the products above.
C, DSP, Assembler, Development, Native, Gsm, Mode, Software, Design, System Design, Testing, Support, Implementation, Audio, Mac, Budget
1994 - 1994
job
Software Engineer
PA Consulting Group Cambridge.
• Implementation of the GSM full-rate speech codec as part of a proving program for client's GSM development chipset, including identifying and debugging faults in a new DSP design. Full DAI testing software implemented both on target hardware and PC platform, using C and client's DSP assembler.
Design, C, Implementation, Hardware, Testing, Development, Software, Assembler, DSP, Gsm, PC
1992 - 1994
job
Software Engineer
Cambridge Neurodynamics Ltd.
• Design and implementation of a vehicle number plate recognition using neural networks. This project involved designing a real-time control system for a multiple processor DSP system.
• Design and implementation of a real-time single and multi-zone non-linear adaptive predictive controller using neural networks.Presented paper on this design at IEE Control '94 conference.
• Design and implementation of a real-time single and multi-zone non-linear adaptive predictive controller using neural networks.Presented paper on this design at IEE Control '94 conference.
Design, Innovation, Implementation, Neural networks, Software, DSP
1988 - 1992
job
Software Engineer
Fairhurst Instruments Ltd. Dean Court.
• Design and implementation of a help-desk call logging system using a proprietary relational database system. System administrator on a five-site network, including design, implementation and maintenance of several bolt-on database/accounting utilities for the sites' stock control and financial accounting packages.
Design, Database, Network, Implementation, Software, Administrator, Utilities
My education
1989
-
1992
University of Cambridge, Churchill College
Masters, Electrical and Information Sciences
Masters, Electrical and Information Sciences
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